1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a delay locked loop.
2. Related Art
A semiconductor apparatus is operated by a clock is synchronization system, in order to guarantee a high-speed operation without an error. At this time, when an external clock signal is used inside the semiconductor apparatus, clock skew caused by an internal circuit occurs in data outputted from the semiconductor apparatus. Therefore, a delay locked loop is provided to generate a delay locked loop (DLL) clock signal by compensating for a modeled delay value tREP obtained by modeling a delay amount of the internal circuit of the semiconductor apparatus, that is, a delay amount of a path through which data is outputted. Inside the semiconductor apparatus, the DLL clock signal may be used to output data to the outside in synchronization with an external clock signal.
FIG. 1 is a block diagram of a conventional delay locked loop.
The delay locked loop of FIG. 1 includes a variable delay unit 1, a delay model unit 2, a phase comparison unit 3, and a delay code generation unit 4.
The variable delay unit 1 is configured to control a delay amount of a reference clock signal REFCLK in response to a delay code D_CODE and generate a DLL clock signal DLLCLK.
The delay model unit 2 is configured to delay the DLL clock signal DLLCLK by a modeled delay value tREP and generate a feedback clock signal FBCLK.
The phase comparison unit 3 is configured to compare the phases of the feedback clock signal FBCLK and the reference clock signal REFCLK and generate a phase detection signal UP_DN according to the comparison result. The phase detection signal UP_DN is updated at a predetermined period until the feedback clock signal FBCLK and the reference clock signal REFCLK have the same phase. When the feedback clock signal FBCLK and the reference clock signal REFCLK have substantially the same phase, the delay locked loop is locked.
The delay code generation unit 4 is configured to generate a delay code D_CODE in response to the phase detection signal UP_DN.
In a system which operates at high speed and frequently performs a power down mode to reduce power, a delay locked loop needs to be locked within a short time such that the semiconductor apparatus normally operates.